I seek to broaden my perspective on world. Labs and practical kept me exited during school and collage days. Countless nights had spent on Electronics and Physics during back in 90s. Engineering collage introduced me into Image Processing and it happened to be my long lasting passion. I had times where I dived deep into subjects like startups, phycology, and evolution.


Quite interested in ASIC Design Verification and related technologies. System Verilog, UVM (Universal Verification Methodology), Machine-Learning keeps me going.



And this was what kept me going so far.

PCIe Gen 4 and NVMe Memory Controller SSD SoC Verification

October 1, 2016

SoC Verification, System Verilog, UVM, Toggle Coverage

PCIe Gen 3 and SCSIe Memory Controller Host Sub-system Verification

March 1, 2013

System Verilog, AVIP, Palladium, UVM, SCEMI PIPE, TLM

PCIe Gen 3 and NVMe Memory Controller Full Chip Verification

October 1, 2012

System C, System Verilog Assertion, AVIP, Palladium, SCEMI PIPE, TLM

PCIe Gen 2 and AHCI Memory Controller Host Sub-system Verification

November 1, 2011

Development of the AHCI driver in with Accelerated-Verification-IP for Cadence Palladium Emulator

PhD Electronics and Communication

March 1, 2010

NAND Memory Controller Verification

January 1, 2010

SOC verification

Joined in Samsung Electronics Ltd., South Korea

December 1, 2009

Senior Engineer

Wimax Physical layer IP

November 1, 2008

Design and implementation of Wimax (802.16e) PHY Layer (Baseband) Encoder and Decoder for Mobile station in SOC with FPGA & TMS320C5510

LDPC – Low Density Parity Check IP

August 1, 2008

Design & implementation of Wimax LDPC forward error correction code.

Timing Synchronisation & Channel estimation IP

April 1, 2008

Design & implementation of Wimax CPE side Timing Synchronisation and Channel estimation in RTL

Joined in Mahindra Singapore Ltd., Changi, Singapore

March 1, 2008

Senior Engineer

JPEG2000 Codec Hardware

August 1, 2007

JPEG2000 Encoder and Decoder in 90nm ASIC

H.264 Codec Hardware

February 1, 2007

H.264 High Profile Encoder and Decoder in SOC

H.264 Codec C Model

December 1, 2006

Design and implementation of H.264 Baseline Profile Encoder and Decoder model in C

CAVLC Decoder on FPGA-StratixII

July 1, 2006

CAVLD (VLC decoding module of H.264 decoder) on to StratixII FPGA

Joined in Tata Elxsi Ltd., Bangalore, India

June 1, 2006

Senior Engineer

H.264 on OMAP ARM9

June 1, 2005

H.264/AVC Baseline Video Encoder on OMAP 5912 and C55x-specific optimization

Joined in Satyam Computer Services Ltd., Bangalore, India

May 1, 2005

Software Engineer

M.Tech. VLSI(Very Large Scale Integration)

March 1, 2005

B.E. Electronics and Communication

March 1, 2003


Would you like to ask me a doubt? Or you just want to say a hello?
Don’t wait. I would love to hear from you. Contact me right away.