Quite interested in ASIC Design Verification and related technologies. System Verilog, UVM (Universal Verification Methodology), Machine-Learning keeps me going.
UVM – Universal Verification Methodology
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, and Synopsys.
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Developing Accelerated TestBench (ATB). C++, System-C or UVM. whats your choice for HVL layer?
For last couple of years myself and my team is developing Accelerated TestBench for our multi-million SoC with several ARM processors on it. This whole concept of simulation acceleration is exciting for me because of the long waiting hours on simulation environment is reduced into few minutes in emulation setup. However, developing a testbench needs a unique approach since the …
About
And this was what kept me going so far.
PCIe Gen 4 and NVMe Memory Controller SSD SoC Verification
October 1, 2016
SoC Verification, System Verilog, UVM, Toggle Coverage
PCIe Gen 3 and SCSIe Memory Controller Host Sub-system Verification
March 1, 2013
System Verilog, AVIP, Palladium, UVM, SCEMI PIPE, TLM
PCIe Gen 3 and NVMe Memory Controller Full Chip Verification
October 1, 2012
System C, System Verilog Assertion, AVIP, Palladium, SCEMI PIPE, TLM
PCIe Gen 2 and AHCI Memory Controller Host Sub-system Verification
November 1, 2011
Development of the AHCI driver in with Accelerated-Verification-IP for Cadence Palladium Emulator
PhD Electronics and Communication
March 1, 2010
NAND Memory Controller Verification
January 1, 2010
SOC verification
Joined in Samsung Electronics Ltd., South Korea
December 1, 2009
Senior Engineer
Wimax Physical layer IP
November 1, 2008
Design and implementation of Wimax (802.16e) PHY Layer (Baseband) Encoder and Decoder for Mobile station in SOC with FPGA & TMS320C5510
LDPC – Low Density Parity Check IP
August 1, 2008
Design & implementation of Wimax LDPC forward error correction code.
Timing Synchronisation & Channel estimation IP
April 1, 2008
Design & implementation of Wimax CPE side Timing Synchronisation and Channel estimation in RTL
Joined in Mahindra Singapore Ltd., Changi, Singapore
March 1, 2008
Senior Engineer
JPEG2000 Codec Hardware
August 1, 2007
JPEG2000 Encoder and Decoder in 90nm ASIC
H.264 Codec Hardware
February 1, 2007
H.264 High Profile Encoder and Decoder in SOC
H.264 Codec C Model
December 1, 2006
Design and implementation of H.264 Baseline Profile Encoder and Decoder model in C
CAVLC Decoder on FPGA-StratixII
July 1, 2006
CAVLD (VLC decoding module of H.264 decoder) on to StratixII FPGA
Joined in Tata Elxsi Ltd., Bangalore, India
June 1, 2006
Senior Engineer
H.264 on OMAP ARM9
June 1, 2005
H.264/AVC Baseline Video Encoder on OMAP 5912 and C55x-specific optimization
Joined in Satyam Computer Services Ltd., Bangalore, India
May 1, 2005
Software Engineer
M.Tech. VLSI(Very Large Scale Integration)
March 1, 2005
B.E. Electronics and Communication
March 1, 2003
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