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Memory Management
In hardware architecture,
the individual stages have been pipelined for simultaneous
processing of macroblocks. Each pipeline stage is fed by a
macroblock buffer containing the current macroblock header
and data; the results of each stage are saved into another
macroblock buffer for input to the next pipeline stage. In
order to minimize dependencies between the pipeline stages,
each macroblock buffer should be implemented as a ping-pong
buffer of two macroblocks: the macroblock currently being
stored by the prevous stage, and the macroblock being read
by the current stage.
1. In the input and output
of the pipeline stage there will be one input and output
memory. Since the different stages in the pipeline processes
concurrently, a ping-pong buffer management has to be
deployed. A Ping-Pong buffer is used in a data transfer that
contains two separate buffers, while one buffer is receiving
new data the other buffer is deleting the previous data.
This type of memory management ensures a real time
processing.
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2. During the calculation
for required memory in the initial stages of the design, one
has to incorporate these ping-pong buffers as well.
3. The ping-pong memory
mostly doubles the memory requirements. If the design cannot
afford ping-pong memory, then the process in the pipes has
to complete its processing in half the clock cycles allotted
for one pipe.
4. In the design,
consideration for the reduction in the memory usage is
useful in ASIC as well as in FPGA design. In ASIC, the
costliest component is memory, hence the reduction will help
in reducing production cost. In FPGA, accessing large chunks
for RAM by different circuits may introduce more routing
delay that results in low operational frequency.
5. In ASIC design, it is
recommended to use 'single port RAMs' instead of FIFOs
throughout the design to bring the memory requirement under
check. The FIFOs requires 'two port RAMs' which takes double
the area of 'single port RAMs'.
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