H.264 Video Codec on FPGA

In the search for ever better and faster video compression standards H.264 was created. With it arose the need for hardware acceleration of its very computationally intensive parts.

Considering the implementation of complex video codec such as H.264, the hardware have high computational and memory bandwidth capabilities that are essential to real-time video processing systems, when compared with DSP processors. The products like Digital video recorders, Video wireless devices, Video surveillance systems, Hand held HDTV video cameras, requires low power high performance implementation.

The important  step towards the realization of Video Codec on Hardware is to prototype the Codec on FPGA.

Let it be a baseline profile or a high profile, only a carefully designed  architecture can meet the real time requirements. This document aid you to design a successful architecture for H.264 encoder. If you are recently started with H.264, please refer the tutorial pages.

FPGA RTL Code for H.264 Encoder
This is a open-source RTL VHDL code for H.264 Encoder.
Before usage please check the licensing of the code.

FPGA RTL Code for H.264 Decoder
This is a open-source RTL Verilog code for H.264 Decoder.
Before usage please check the licensing of the code. 

You can consult the author Tony Gladvin George for the implementation of latest Video CODECs on FPGA.

Features in H.264 and implementation feasibilities

Encoder architecture for H.264 Video encoder in FPGA

Important modules and complexity estimates

Memory Management in the FPGA Codec

H.264 on FPGA IP Vendors

Optimization methods for real time performance